The present invention relates to a CCD delay line of low noise level and low power consumption.
As disclosed in U.S. Pat. No. 3,986,198, the CCD delay line has already been put into practice for processing the signals for a video camera or the like. This CCD delay line has a problem in the requirement of a high driving power so that it obstructs a long-time image pickup of such a video camera when it is driven by a battery. The driving power P is expressed basically by the following equation: EQU P=fCV.sup.2 ( 1),
wherein: f is a clock frequency; C is a full gate capacity; and V is a clock amplitude (i.e., the peak-to-peak value of the voltage). In the case of f=10 MHz, C=200 pF and V=10 V, for example, P=0.2 W. Let the case be assumed in which four such CCD delay lines are used. Then, the CCD delay lines will require about 0.8 W, which is a high burden on a video camera which normally has a total power consumption of about 3 W.
For a lower power consumption, as found from equation (1), it is necessary to reduce the gate capacity C or the clock amplitude V. With this reduction of either value, however, the amount of signal charge to be handled drops to degrade the S/N ratio.